C
C#•3mo ago
noreon

Computer Science - Computer Architecture

On a 64 bit system (where the bus length and word size are 64 bits) how would we determine the ammount of addressable locations in say 4gb of memory? is is the case of size of memory / word length = ammount of memory locations? so on a 64 bit system where we have 4 gb of ram, there are 536,870,912 locations each holding 64 bits?
74 Replies
mtreit
mtreit•3mo ago
No, modern computers are always byte addressable. The native word size has nothing to do with how much memory is addressable. A single memory address points to exactly one byte in memory.
leowest
leowest•3mo ago
MODiX
MODiX•3mo ago
viceroypenguin
yes, 32b - 3b = 29b = 512mm = 536...
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mtreit
mtreit•3mo ago
That's an odd way of stating it if the question is about how many addressable locations there are. A memory address doesn't point to a 64-bit or 32-bit value, it points to a single byte. That byte might be the start of a 32-bit or 64-bit number as far as the software using the memory is concerned, but it certainly doesn't have to be.
Petris
Petris•3mo ago
I think Java actually has their addresses multiplied by 4 to handle more than 4GB on 32bit
thadhouse#1061
thadhouse#1061•3mo ago
Its actually not for 32 bit purposes. Its for 64 bit processes to be able to use the same amount of memory as 32 bit processes. While having a lot more memory actually available. https://wiki.openjdk.org/display/HotSpot/CompressedOops
noreon
noreon•3mo ago
this is purely for the sake of computer architecture so not involving any languages like java. Let me just clarify what i meant ane maybe someone can correct me if im wrong. on a 64 bit (8 byte) system, with main memory the size of 4GB (2^32), the amount of addressable locations (or containers for data) is determined by: address locations = main memory size (4gb) / word size (8 byte). this gives us 536 870 912 memory locations, each capable of holding 8 byte words (or 64 bits). address location can represent 2 ^ 64 bits of data. that what i thought and i think that viceroypenguin basically confirmed my theory, although in a true sccientific fashion, i can never be 100% certain that i mcorrect
mtreit
mtreit•3mo ago
Addressable locations are not related to word size because each address is to a single byte, not a single word
noreon
noreon•3mo ago
are you sure that this is correct. youre not very clear with your answers. perhaps you could elaborate again, in memory size of 4 gb (2^32) each address location holds 8 bytes of data therefore (4gb) 2^32 / (8bytes) 2^3 = 2^29 or 536 870 912 addressable locations each location can represent 64 bits of data, but in most cases it doesnt need to use all of it.
mtreit
mtreit•3mo ago
Each address points to one byte of data I think that's the disconnect Every byte in memory has an address Imagine a byte array (like an ascii string) and imagine how you can walk that string character by character. How would that work with the scheme you are describing?
noreon
noreon•3mo ago
so if a single address points to a single byte of data, then in 4 gb of ram there should be 4 gb / 1 byte of addressable locations?
mtreit
mtreit•3mo ago
Yes
noreon
noreon•3mo ago
4gb( 2^32) / 1 byte (2^0) = 2^32 or approximately 4 billion addressable locations? so the ammount of addressable locations is basically the ammount of the ram itself so, if there is a 64 bit system, with a 64 bit word, then that word has to be split up into 8 different address locations?
mtreit
mtreit•3mo ago
Yes, each byte of the 8 byte word has its own address. In practice, you just take the address of the first byte and the language you are programming in handles the rest based on the size of the data type
noreon
noreon•3mo ago
just to clarify this isnt related to any programming language. im a little confused now as
noreon
noreon•3mo ago
No description
mtreit
mtreit•3mo ago
Pointer arithmetic in C is a good illustration. If you have a pointer to an array of int, incrementing the pointer advances it by four bytes. If you have a pointer to an array of char (byte in C# terms) incrementing the pointer advances by one byte. The language knows the size of the data types.
noreon
noreon•3mo ago
this basically confirms what penguin said
mtreit
mtreit•3mo ago
This is saying the size of the address
noreon
noreon•3mo ago
this sould confirm that a single address location is 8 bytes
mtreit
mtreit•3mo ago
Not the size of what the address points to Again modern computers are always "byte addressable" meaning each address is to a single byte
noreon
noreon•3mo ago
No description
noreon
noreon•3mo ago
the size of the address itself is a byte so if an address location can hold 8 bytes, 1 byte can be for the address itself, 4 bytes can be for the data and the other 3 can be used for whatever
mtreit
mtreit•3mo ago
This is completely wrong
noreon
noreon•3mo ago
yea, chat gpt can be very wrong. but this is also what penguin confirmed in main chat, thats why im still sitting here struggling to grasp this.
mtreit
mtreit•3mo ago
@viceroypenguin | 🦋🐧🌟 can you clarify Driving to work, will be offline for a bit
noreon
noreon•3mo ago
no worries. thanks for the help dude 🙏🏼
mtreit
mtreit•3mo ago
Computerphile
YouTube
Where did Bytes Come From? - Computerphile
Why do we have 8 bits in a byte? Professor Brailsford on the origins of the humble byte. Why Use Binary?: https://youtu.be/thrx3SBEpL8 Babbage's Puzzle: https://youtu.be/2qzjBmK0_20 Initial Orders II: https://youtu.be/nc2q4OOK6K8 The Font Magicians: https://www.youtube.com/watch?v=jAdspOtgciQ Colossus and Bletchley Park: https://www.youtube...
noreon
noreon•3mo ago
gotcha
viceroypenguin
viceroypenguin•3mo ago
oh, this is a completely different question than what you originally asked. the question you originally asked, rephrased, is: if i have a 4GB-long array of pointers, how many pointers are in the array (aka how long is the array in terms of units). and the answer to that is 2^29 (or 512Mi or 536,xxx,xxx).
noreon
noreon•3mo ago
no
noreon
noreon•3mo ago
No description
viceroypenguin
viceroypenguin•3mo ago
the question I htink you're trying to ask is: if i have 4GiB of RAM, with a word size of 64 bits (8 bytes), then how many addressable locations are in memory. which the answer is the same, but it means something completely different. but pointer size and word size are not the same thing
noreon
noreon•3mo ago
^ Literally the same question with a little less details
noreon
noreon•3mo ago
its literally the exact same question...
viceroypenguin
viceroypenguin•3mo ago
it is not
noreon
noreon•3mo ago
...
viceroypenguin
viceroypenguin•3mo ago
you may not understand it. but they are different questions. now.... if you have 4GiB of RAM, then you don't need 8 byte pointers; 32b (4 byte) pointers will work, regardless of the word size the size of the pointer has nothing to do with the size of the addressable location.
noreon
noreon•3mo ago
what pointers
viceroypenguin
viceroypenguin•3mo ago
the size of the pointer has to do with how many addressable locations you want to address. if you ahve 4GiB RAM, you cannot have more than 2^32 addressable locations, so you don't need 8 byte pointers
noreon
noreon•3mo ago
whats a pointer xd
viceroypenguin
viceroypenguin•3mo ago
ok, so now we're getting into why you don't understand. haha
noreon
noreon•3mo ago
would you like me to ask the question one last time so that we can start from scratch?
viceroypenguin
viceroypenguin•3mo ago
ok, let's go back to the beginning here's the thing whether system is 64 bit or 32 bit has nothing to do with how many addressable locations ar ein memory
noreon
noreon•3mo ago
ok were getting somewhere 😄
viceroypenguin
viceroypenguin•3mo ago
the ISA determines what the addressable locations are. not the word size
noreon
noreon•3mo ago
i see
viceroypenguin
viceroypenguin•3mo ago
in x86 and x64 ISAs, the addressable location is the byte.
noreon
noreon•3mo ago
so a memory location is 1 byte in size?
viceroypenguin
viceroypenguin•3mo ago
in x86/x64
noreon
noreon•3mo ago
yes : ) gotcha
viceroypenguin
viceroypenguin•3mo ago
in others, it may be 4B or 8B
noreon
noreon•3mo ago
which are the most popular architectures today correct? or standard atleast
viceroypenguin
viceroypenguin•3mo ago
x64 and ARM are the two most popular today, correct
noreon
noreon•3mo ago
soo, in that case
viceroypenguin
viceroypenguin•3mo ago
ARM uses a 4B or 8B addressable location.
noreon
noreon•3mo ago
so if we have 4gb of ram in order to find the ammount of locations we use 4gb / 1 byte which is approx 4 billion addressable locations basically the ram size itself ?
viceroypenguin
viceroypenguin•3mo ago
now question: why is the number of addressable locaitons important to you? correct
noreon
noreon•3mo ago
ahh. damn! gotcha
viceroypenguin
viceroypenguin•3mo ago
because keep in mind that the representation of that addressable location is not necessarily the same as the the number of addressable locations
noreon
noreon•3mo ago
um, not really important. i just wanted to build a more borad understanding.
viceroypenguin
viceroypenguin•3mo ago
because even though you can't address every byte of RAM in ARM, the representation of that location is still at the byte level aka location 0x4 is still represented by 0x4 instead of 0x1
noreon
noreon•3mo ago
so if there is a 64 bit word, lets say hypothetically that we use the entire 64 bits for endocing data, then it has to spread over 8 different address locations (8 bytes) i think mtreit already confimed that
mtreit
mtreit•3mo ago
Ok I don't know anything about ARM, you're saying you can't address individual bytes on ARM? How do strings work?
viceroypenguin
viceroypenguin•3mo ago
IIRC… you have to load up the 32b word at a time and process it that way with shifts and such.
noreon
noreon•3mo ago
actually, im just going ovber computer architecture for my cs degree, im a 1st year. were going over caching, paging and etc. still kinda uncertain about the whole concept of blocks, frames stots and flags etc shits really interesteing but hard
viceroypenguin
viceroypenguin•3mo ago
Yeah, chip caching is gonna be really interesting. L1, L2, L3 etc
mtreit
mtreit•3mo ago
Stack Overflow has some comments like this:
ARM (like most modern ISAs) uses byte addressing. (ARM does have a feature to allow bit-level addressing, mapping a section of the address space (bit band) for this. Such is primarily intended for memory-mapped I/O where atomic bit-level addressing can be useful since accesses to I/O devices can have side effects (so a byte read to get a single bit could generate unintended side effects for the seven other bits read and a read-modify-write sequence to change one bit could have unintended effects).
Is that just completely wrong?
noreon
noreon•3mo ago
can anyone just confirm that this is correct: cache and ram is split into blocks holding 2^n data words. (cache blocks are called slots). pages are blocks of data transferred from seccondary memory to main memory. but what are frames and flags?
viceroypenguin
viceroypenguin•3mo ago
more likely to be right than me. maybe i'm mixing it with another ISA
mtreit
mtreit•3mo ago
"Secondary memory" meaning disk storage or the like, presumably. Also not sure about ram being "split into blocks", but maybe that's talking about hardware details that are beyond my knowledge (I'm not a hardware guy at all.) Frames and flags...need more context.
noreon
noreon•3mo ago
ahh, cheers for the help anyways. I think thats plenty you guys explained to me in terms of the address locations etc. i really appreciate that! 🙏🏼
mtreit
mtreit•3mo ago
No problem, glad you're learning 🙂
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