Has anyone experience with the integrated pcie block from the xilinx 7 series fpga's?
Has anyone experience with the integrated pcie block from the xilinx 7 series fpga's? I cannot get is to identify as an memory controller. Of course, I selected it in the configuration dialog, but my cpu always reports it as an simple communication controller.
Solution
I just tried, and now it works again, without this additional delayed-reset-woodoo I copied from another project. The main culprit was, that I had a wrong assignment
user_led(0 downto 1) <= some_signal(1 downto 0)
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