Has anyone experience with the integrated pcie block from the xilinx 7 series fpga's?

Has anyone experience with the integrated pcie block from the xilinx 7 series fpga's? I cannot get is to identify as an memory controller. Of course, I selected it in the configuration dialog, but my cpu always reports it as an simple communication controller.
Solution:
I just tried, and now it works again, without this additional delayed-reset-woodoo I copied from another project. The main culprit was, that I had a wrong assignment user_led(0 downto 1) <= some_signal(1 downto 0) that led to all kinds of strange behavior in unrelated parts of the project.
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8 Replies
Navadeep
Navadeep2mo ago
is your FPGA side acting as edge or root?
Navadeep
Navadeep2mo ago
I have explore this on Zynq Ultrascale+ where there is a specific mapping to the hard IP in the SoC and custom block is implementable as well on the FPGA fabric. In spartan 7 I suppose you're adding it from the IP repository of vivado block designer?
Navadeep
Navadeep2mo ago
x number of lane selection in the card(hardware wiring) and reset line mapping is all it takes for the Edge device alongside receiving the 100MHz clock.
Manuel
Manuel2mo ago
@Navadeep acting as edge. Porting an existing project from virtex 5 to artix 7. Yes, added from IP repository, configured it. It shows up on the cpu, but as simple communication controller (class_code 0700) instead of the configured memory controller (class_code 0500). I checked all settings, grepped for 0700 in the sources, but have no Idea, why it identifies as such. Other settings are fine.
Manuel
Manuel2mo ago
Providing an additional delayed reset after power on fixed the problem.
techielew
techielew2mo ago
@Navadeep @Manuel we moved this discussion here. Did you get this resolved, if so, what was the fix? If not, let's get this sorted.
Navadeep
Navadeep2mo ago
Good to know! So it was with the startup sequence of the protocol...
Solution
Manuel
Manuel2mo ago
I just tried, and now it works again, without this additional delayed-reset-woodoo I copied from another project. The main culprit was, that I had a wrong assignment user_led(0 downto 1) <= some_signal(1 downto 0) that led to all kinds of strange behavior in unrelated parts of the project.
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