Does anyone have experience with directly mapping FPGA memory to the microcontroller's memory space
@Middleware & OS I'm redesigning an FPGA for faster SPI communication. The current design utilizes a DMA controller to read data from internal RAM, but I'm experiencing some performance issues.
I suspect the current bottleneck might be the data transfer between the internal RAM and the DMA controller.
I'm considering directly mapping the FPGA memory containing the data to the microcontroller's memory space for maybe a faster transfers.
I've reviewed some resources on memory-mapped I/O for FPGAs, but haven't found specific examples related to SPI communication. My question is : 1. Does anyone have experience with directly mapping FPGA memory to the microcontroller's memory space for SPI communication? 2. Are there any specific challenges or considerations I should be aware of with this approach? Good evening Devs, I need your humble opinion(s)🙏
I've reviewed some resources on memory-mapped I/O for FPGAs, but haven't found specific examples related to SPI communication. My question is : 1. Does anyone have experience with directly mapping FPGA memory to the microcontroller's memory space for SPI communication? 2. Are there any specific challenges or considerations I should be aware of with this approach? Good evening Devs, I need your humble opinion(s)🙏
Solution:Jump to solution
Spartan 6 don't come with hard processors. Are you using their legacy ISE suite or Vivado?
If you are on ARM Cortex Processor, it is likely that you're on a 7 series SoC. Take a look at https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133 and follow up blog where designing with AXI DMA, configuration, streaming is described....
PYNQ
Tutorial: PYNQ DMA (Part 1: Hardware design)
PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you...
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What chip you are using ?
I'm making use of Xilinx Spartan-6 chip @youcef_ali
You are using the softcore microblaze. ?
Well,I'm not using a MicroBlaze in my project, it's definitely an option for trying out a softcore processor in the future. But I'm working with the hard-core ARM processor that comes with the Spartan-6 series. @youcef_ali
I didn't work with Spartian before. I used Zynq7000 and artix, does the sprtian have Zynq 7 processing system?
Solution
Spartan 6 don't come with hard processors. Are you using their legacy ISE suite or Vivado?
If you are on ARM Cortex Processor, it is likely that you're on a 7 series SoC. Take a look at https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133 and follow up blog where designing with AXI DMA, configuration, streaming is described.
PYNQ
Tutorial: PYNQ DMA (Part 1: Hardware design)
PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you...
Thanks @Navadeep ...This your educative suggestion will be helpful to my project.