How can I create and implement DDR memory in Verilog on an FPGA?
I want to create a DDR memory using Verilog and implement it on an FPGA. I wanted to ask for resources that could help me get started. I have no idea of how DDR RAM works, I browsed some sourcces and came across DFI protocol, DDR PHY IP, but I didn't understand much. I want a basic application note or white paper that can get me started on understanding the memories.
The main goal is to create a whole processor with all features possible below.
I have created a RISC processor with custom ISA, which is 16-bit. I want to increases its functionality.
I have implemented 2-bit branch predictor in it.
To be done:
Adding UART to my processor so that I can write to the Data memory directly instead of mentioning the instructions directly in the Verilog code of the data memory itself. (designed, yet to be tested)
The next step that I think, should be to integrate a RAM to it.
Add Cache and design whole memory sub-system.
I also want to create a SPI Flash so that I can put my custom BIOS in it.
Any suggestions to what could I do more on my processor?
@Middleware & OS
The main goal is to create a whole processor with all features possible below.
I have created a RISC processor with custom ISA, which is 16-bit. I want to increases its functionality.
I have implemented 2-bit branch predictor in it.
To be done:
Adding UART to my processor so that I can write to the Data memory directly instead of mentioning the instructions directly in the Verilog code of the data memory itself. (designed, yet to be tested)
The next step that I think, should be to integrate a RAM to it.
Add Cache and design whole memory sub-system.
I also want to create a SPI Flash so that I can put my custom BIOS in it.
Any suggestions to what could I do more on my processor?
@Middleware & OS
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